The present invention relates generally to design structures for dynamic data paths and, more particularly, to a design structure for implementing dynamic data paths with interlocked keeper and restore devices.
Dynamic logic is one type of circuit design approach that is used to increase digital circuit speed, as compared to static complementary metal oxide semiconductor (CMOS) logic, for example. A CMOS gate is a fully complementary logic gate using both p-type and n-type devices configured to implement a desired logic function (e.g., a simple inverter). Static CMOS logic gates require large fan-in, which in turn causes large gate input capacitances that slow down the logic circuit. Furthermore, static logic gates use relatively slow p-type metal oxide semiconductor (PMOS) devices to implement a pull-up network, which further increases the capacitance of the gate input and slows rise times.
In dynamic logic circuits, a PMOS pull-up network is replaced by a single clocked PMOS transistor. Each clock cycle is divided into two phases, a “precharge” phase and an “evaluate” phase. During the precharge phase, an output node is unconditionally precharged to a high logic state. Then, during the evaluate phase, the output node either remains high or is conditionally discharged to low, depending on the current logic output level. The logic function is implemented by a network of n-type pull down transistors, which are controlled by their respective gate inputs in order to either maintain or discharge the voltage at the output node.
A transition period corresponds to the time between when the node is precharged and when the input signal is evaluated. During this time, the node may not be driven by any component but is instead “floating.” As a result, the node is susceptible to leakage paths through the pull down devices, which could result in an erroneous evaluation of the input signal during the subsequent evaluation period. Thus, one existing approach to preventing false evaluations is the use of a “keeper” circuit that utilizes a pull-up transistor to maintain the precharge node at a desired logic level during the transition period. In this approach, the pull-up PMOS transistor of the keeper is coupled between the supply voltage source and the precharged node, with the gate of the transistor being coupled to the inverted node voltage. When the precharge node is precharged high, the inverter provides a logic low signal to render the keeper PMOS transistor conductive and thus maintain the precharge node high even after the precharge phase is complete.
Unfortunately, the increased leakage current associated with scaled technologies has forced designers to increase the size of the keeper devices in dynamic circuits to maintain nodes at the precharge state. In addition, the evaluation stacks must be made with longer device lengths or higher voltage thresholds to substantially reduce the leakage. Conversely, if the keeper is too strong, the pull down devices will have greater difficulty pulling down the output node during an evaluation phase. As such, the resulting slower performance of dynamic circuit topologies (as compared to static circuits) would arguably no longer justify the implementation of the dynamic logic. Further, self-resetting techniques typically employed for dynamic data paths are becoming very difficult to control because of the larger device variations and poor control of the evaluation and precharge periods. Accordingly, it would be desirable to be able to provide an improved dynamic data path that maintains acceptable levels of robustness.